System architects working on system-on-chip (SoC) designs are hampered by the dearth of reliable ways to evaluate an architecture or verify hardware and software together. Fortunately, SystemC, an ...
To achieve higher quality on multimillion gate designs and high-speed ASICs, manufacturers are relying on structured DFT (design-for-test) methodologies such as scan, at-speed test, scan compression, ...
TOKYO, May 08, 2025 (GLOBE NEWSWIRE) -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) today unveiled SiConic Test Engineering (TE), the newest addition to the SiConic ...
Developing an automated production test solution for current and next-generation complex RF SIP/SOC devices is an increasingly difficult task. Both the test program and the device interface board (DIB ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results