All
Web
Search
Images
Videos
Shorts
Maps
More
News
Shopping
Flights
Notebook
Report an inappropriate content
Please select one of the options below.
Not Relevant
Offensive
Adult
Child Sexual Abuse
Verilog
Coding Tutorial
Verilog
Basics
VHDL
Programming
NPTEL Verilog
Lectures
SystemVerilog
Tutorials
Verilog
Training
Verilog
HDL Tutorial
USB Verilog
Example
Verilog
Inverter
How to Start
Verilog
Verilog
Introduction
Clock Divider
Verilog
Verilog
Course
Verilog
Code
Length
All
Short (less than 5 minutes)
Medium (5-20 minutes)
Long (more than 20 minutes)
Date
All
Past 24 hours
Past week
Past month
Past year
Resolution
All
Lower than 360p
360p or higher
480p or higher
720p or higher
1080p or higher
Source
All
Dailymotion
Vimeo
Metacafe
Hulu
VEVO
Myspace
MTV
CBS
Fox
CNN
MSN
Price
All
Free
Paid
Clear filters
SafeSearch:
Moderate
Strict
Moderate (default)
Off
Filter
Verilog
Coding Tutorial
Verilog
Basics
VHDL
Programming
NPTEL Verilog
Lectures
SystemVerilog
Tutorials
Verilog
Training
Verilog
HDL Tutorial
USB Verilog
Example
Verilog
Inverter
How to Start
Verilog
Verilog
Introduction
Clock Divider
Verilog
Verilog
Course
Verilog
Code
0:11
YouTube
verilog_code
Build a Half Adder in Verilog Using assign | Verilog Dataflow Modeling
Learn how to build a 1-bit Half Adder in Verilog using Dataflow Modeling and the assign keyword. In this tutorial, you'll understand: 🔹 What a Half Adder is 🔹 Sum and Carry logic 🔹 XOR and AND gates 🔹 Verilog assign statements 🔹 Half-Adder truth table 🔹 RTL representation 🔹 How to verify the design Key equations: Sum = A ...
235 views
1 month ago
Watch full video
Shorts
6:39
106.9K views
Học Ngành Vi Mạch Bán Dẫn: Cơ Hội và Thách Thức
thayquyethuongnghiep
0:22
290 views
Master the 2:1 Multiplexer! 🔀⚡ | Verilog Code + Testbench + Waveform (Vivado FPGA
Sly Fox electronics
Verilog Tutorial
1:03
Trigger Events on Time with @timer operator #eda #cadence #chipdesign
YouTube
Cadence Design Systems
279 views
2 months ago
0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL)
YouTube
Sly Fox electronics
635 views
6 months ago
0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL) [short]
YouTube
Sly Fox electronics
84 views
3 months ago
Top videos
1:13
Resistor Modeling in Verilog-A #verilog #vlsi
YouTube
Cadence Design Systems
654 views
2 months ago
0:18
Gate-Level Modeling in Verilog: Primitives Explained + Quiz 🔥
YouTube
verilog_code
1 month ago
0:11
Verilog wire Explained i | Connecting Signals in Verilog
YouTube
verilog_code
100 views
1 month ago
Verilog Examples
2:52
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
YouTube
Chip Logic Studio
688 views
5 months ago
1:07
Digital Versus Analog: Inverter Modeling, Unpacked #vlsi #coding #asicdesign
YouTube
Cadence Design Systems
633 views
3 months ago
2:57
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
YouTube
Chip Logic Studio
1.5K views
5 months ago
1:13
Resistor Modeling in Verilog-A #verilog #vlsi
654 views
2 months ago
YouTube
Cadence Design Systems
0:18
Gate-Level Modeling in Verilog: Primitives Explained + Quiz 🔥
1 month ago
YouTube
verilog_code
0:11
Verilog wire Explained i | Connecting Signals in Verilog
100 views
1 month ago
YouTube
verilog_code
0:22
Master the 2:1 Multiplexer! 🔀⚡ | Verilog Code + Testbench + Waveform (Vivado FPGA Tutorial) Review
290 views
1 month ago
YouTube
Sly Fox electronics
1:03
Trigger Events on Time with @timer operator #eda #cadence #chipdesign
279 views
2 months ago
YouTube
Cadence Design Systems
0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL)
635 views
6 months ago
YouTube
Sly Fox electronics
0:23
Building a Full Adder the Smart Way 🧠⚡ | Verilog Design Using Half Adders (Simulation + RTL) [short]
84 views
3 months ago
YouTube
Sly Fox electronics
2:52
Verilog Counter Code with Testbench & Simulation | Complete Tutorial for Beginners
688 views
5 months ago
YouTube
Chip Logic Studio
1:07
Digital Versus Analog: Inverter Modeling, Unpacked #vlsi #coding #asicdesign
633 views
3 months ago
YouTube
Cadence Design Systems
2:57
2-bit Adder to 4-bit Adder in Verilog | Structural Modeling + Testbench + Simulation
1.5K views
5 months ago
YouTube
Chip Logic Studio
1:24
Difference between Data types of Verilog and SystemVerilog #cadence #chipdesign
1.1K views
4 months ago
YouTube
Cadence Design Systems
6:39
Học Ngành Vi Mạch Bán Dẫn: Cơ Hội và Thách Thức
106.9K views
Sep 6, 2025
TikTok
thayquyethuongnghiep
0:54
LÀM CHIP KHÓ LẮM SAO? LỘ TRÌNH 6 BƯỚC ĐỂ TRỞ THÀNH KỸ SƯ THIẾT KẾ IC! ⸻ 1. Thiết kế IC là gì? \t•\tThiết kế IC (Integrated Circuit) là quá trình biến ý tưởng thành vi mạch điện tử. \t•\tGồm 2 mảng chính: \t•\tFront-end: Thiết kế logic – viết code mô tả phần cứng (Verilog/VHDL). \t•\tBack-end: Triển khai layout – thiết kế hình dạng vật lý con chip. ⸻ 2. Lộ trình học chi tiết – Từng bước thực tế: Bước 1: Nắm chắc kiến thức điện tử cơ bản \t•\tMạch điện – điện tử: Op-amp, logic gates, CMOS, MOSFET.
65.2K views
Apr 25, 2025
TikTok
ongbobitcoin
3:07
Cuánto ganamos nosotros , los arquitectos en FPGA? #jlcpcb #FPGA #vhdl #fpgaperuana #capsulaelectronica #ingenierofisico #fpgainit #verilog
27.2K views
May 30, 2025
TikTok
capsula.electronica
0:10
Engineer's Guide to Coding and Electronics for Women in STEM
61.9K views
Sep 14, 2023
TikTok
aiszzyelectronics
0:15
FPGA para aplicaciones espaciales
18.2K views
Jun 29, 2025
TikTok
capsula.electronica
0:49
You NEED a complete and up to date LinkedIn profile in 2026. LinkedIn is essentially a search engine for recruiters—if your profile doesn’t have the right keywords, you won’t be found or considered for interviews. To fix this, you need to: 🔑 Target Keywords: Add technical skills like (ex. Python, Verilog, or UVM) to your headline, about section, and experience. 🖼️ Build a Portfolio: Don’t just list skills—post photos of your hardware builds or screen recordings of your code. 📄 Pin Your Resume
4K views
8 months ago
TikTok
engcalebj28
0:35
FPGAs Peruanas: Prototipo Oficial y Entrenamiento
10.7K views
Nov 12, 2024
TikTok
capsula.electronica
0:12
FPGA Project: 7 Segment LED Display with Verilog
5.9K views
Sep 13, 2025
TikTok
furt_tech
See more
More like this
Feedback